报告题目：Memory Centric Optimization: Keep the memory hierarchy but nothing else
报告日期及时间：2017年6月27日10点
报告地点：B403
报告人： Dr. Xian-He Sun
报告人单位： Illinois Institute of Technology (IIT)
报告人简介： Dr. Xian-He Sun is a University Distinguished Professor of Computer Science of the Department of Computer Science at the Illinois Institute of Technology (IIT). He is the director of the Scalable Computing Software laboratory at IIT and a guest faculty in the Mathematics and Computer Science Division at the Argonne National Laboratory. Before joining IIT, he worked at DoE Ames National Laboratory, at ICASE, NASA Langley Research Center, at Louisiana State University, Baton Rouge, and was an ASEE fellow at Navy Research Laboratories. Dr. Sun is an IEEE fellow and is known for his memory-bounded speedup model, also called Sun-Ni’s Law, for scalable computing. His research interests include data-intensive high performance computing, memory and I/O systems, software system for big data applications, and performance evaluation and optimization. He has over 250 publications and 5 patents in these areas. He is a former IEEE CS distinguished speaker, a former vice chair of the IEEE Technical Committee on Scalable Computing, the past chair of the Computer Science Department at IIT, and is serving and served on the editorial board of leading professional journals in the field of parallel processing. More information about Dr. Sun can be found at his web site www.cs.iit.edu/~sun/.
报告摘要： Computing has changed from compute-centric to data-centric. Many new architectures, such as GPU, FPGA, ASIC, are introduced to match computer systems with the applications’ data requirement, and therefore, improve the overall performance. In this talk we introduce a series of fundamental results and their associated mechanisms to conduct this matching automatically, and through both hardware and software optimizations. We first present the Concurrent-AMAT (C-AMAT) data access model to unify the impact of data locality, concurrency and overlapping. Then, we introduce the pace matching data-transfer design methodology to optimize memory system performance. Based on the pace matching design, a memory hierarchy is built to mask the performance gap between CPU and memory devices. C-AMAT is used to calculate the data transfer request/supply ratioat each memory layer, and a global control algorithm, named layered performance matching (LPM), is developed to match the data transfer at each memory layer and thusmatch the overall performance between the CPU and the underlying memory system. The holistic pace-matching optimization is very different from the conventional locality-based system optimization. Analytic results show the pace-matching approach canminimize memory-wall effects.Experimental testing confirms the theoretical findings, with a 150x reduction of memory stall time. Wewill present theconcept of the pace matching data transfer, the design of C-AMAT and LPM, andsome experimental case studies. We will also discuss optimization and research issues related to pace matching data transfer and of memory systems in general.
